Apparatus and method for leadless packaging of semiconductor devices

ABSTRACT

The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

TECHNICAL FIELD

[0001] This invention relates generally to integrated circuit packaging.More particularly, the invention relates to interconnected and leadlesspackaging of semiconductor devices.

BACKGROUND OF THE INVENTION

[0002] Integrated circuits may be contained in a variety of differentpackages before they are integrated into portions of larger electronicsystems. The packages are generally comprised of one or moresemiconductor chips encapsulated in a packaging material. In the case ofpackages containing several chips, the chips are interconnected topermit the chips to cooperatively perform a variety of tasks. Inaddition to the interconnections between the chips within the package,other connections generally extend from the package to permit theintegrated circuit to interact with other portions of a largerelectronic system. The individual chips may be arranged in the packagein a planar configuration with electrical interconnections extendingbetween the chips, but increasingly, the individual chips are arrangedin a vertical stack, with the interconnections extending between thechips comprising the stack. A stacked wafer-level package has numerousadvantages over the planar arrangement, including reducedinterconnection lengths, faster processing times, and substantialreductions in the size and weight of the package.

[0003]FIG. 1 is a partial cross sectional view showing a verticallystacked semiconductor package 10 according to the prior art. The package10 generally includes a substrate 16 that supports a first semiconductorchip 14, which is retained on the substrate 16 by an adhesive layer 18.The adhesive layer 18 is generally comprised of an adhesive compoundhaving a high dielectric strength to prevent electrical communicationbetween the chip 14 and the substrate 16. The chip 14 also generallyincludes one or more bond pads 15 that are electrically coupled to thecircuits formed on the chip 14, which form at least a portion of thesignal input and/or signal output locations for the chip 14. A secondchip 12 is positioned on the chip 14, and is similarly retained on thechip 14 by an adhesive layer 19. The second chip 12 also includes one ormore bond pads 11 that are coupled to the circuits formed on the chip12, and similarly form at least a portion of the signal input and/orsignal output locations for the chip 12. Electrical communicationbetween the chip 12 and the chip 14 is obtained through one or moreelectrically conductive bonding wires 13 that couple the bond pad 11 onthe chip 12 to the bond pad 15 on the chip 14. The bonding wires 13 aregenerally comprised of gold or aluminum, and may be attached to the bondpads 11 and 15 by spot welding, soldering, or by various conductiveadhesive compounds. The bonding wires 13 then generally proceed awayfrom the package 10 to provide an electrical connection to otherportions of a larger electronic system (not shown).

[0004] The prior art semiconductor package 10 shown in FIG. 1 hasnumerous drawbacks, however. For example, the bonding wire 13 generallyhas a relatively long physical length in order to establish the requiredelectrical interconnections between the bond pads 11 and 15. The longphysical length of bonding wire 13 may therefore lead to increasedsignal propagation delays between the chips 12 and 14. Moreover, as thelength of the bonding wire 13 increases, undesirable effects stemmingfrom parasitic capacitance and/or inductance introduced by the bondingwire 13 also increase. Other shortcomings associated with the package 10may include the reflection of at least part of the signal transmittedalong the bonding wire 13 resulting from impedance discontinuities alongthe bonding wire 13, or at the connection interface between the bondingwire 13 and the bond pads 11 and 15. Still further, as the length of thebonding wire 13 increases, the bonding wire 13 becomes increasinglysusceptible to electromagnetic interference since the bonding wire 13may act as an antenna. Still other drawbacks are present in prior artpackage 10. For instance, the size of the bond pads 11 and 15 formed onthe chips 12 and 14 must generally be relatively large to accommodatethe connections formed with the bonding wire 13, which generally limitseither the number of input and output locations, or the number ofcircuits that may be formed on the chips 12 and 14. Moreover, since thebond pads 11 and 15 are generally comprised of gold, the relativelylarge bond pad areas require additional amounts of this material, whichincreases the cost of each unit.

[0005] Other prior art packaging methods mitigate some of the drawbacksassociated with the use of bonding wire interconnections, as describedabove, but introduce still other drawbacks. For example, tape automatedbonding (TAB) methods may be used to establish the interconnectionsbetween vertically stacked semiconductor chips. In TAB, metallicinterconnection traces are formed on a multi-layer polymer tape (notshown). The polymer tape is positioned adjacent to the chips 12 and 14with traces and bonding locations pre-formed on the tape that correspondto the bond pads 11 on the chip 12, and the bond pads 15 on the chip 14.The bonding locations on the tape are then attached to the bond pads 11and 15 on the chips 12 and 14 using conventional joining techniques suchas reflow soldering or conductive adhesives. Although TAB allows thebond pads 11 and 15 on the chips 12 and 14 to be spaced at closerintervals than is generally achievable using the foregoing bonding wiremethod, each chip must generally have its own tape that is individuallypatterned to conform to the bonding pad arrangements on the chips thatare to be interconnected. Consequently, the time and cost associatedwith the design and fabrication of bonding tapes that are individuallyconfigured for each bonding requirement renders TAB methods suitableonly to applications where large production quantities of semiconductorpackages are anticipated.

[0006] The “flip-chip” method represents still another prior artsemiconductor packaging method, which permits the bond pads on adjacentchips to be connected without the use of a discrete interconnectingelements, as employed in the foregoing bonding wire method, or in TAB.In the “flip chip” method, the contact pads of a chip are generallywetted with a reflowable material, such as a solder alloy. The chip isthen brought into facial contact with an adjacent chip or substrate thathas a corresponding set of bond pads. Reflowing the solder alloy in afurnace then electrically and mechanically joins the chips. Although theforegoing method eliminates many of the drawbacks associated with thewire bonding and TAB interconnection methods, other drawbacks areintroduced. For example, the chips thus joined may exhibit significantlydifferent rates of thermal expansion, which may lead to bonding failurebetween the chips. This shortcoming may be further exacerbated by thedegradation of heat conduction through the chip stack that is due to anincrease in the thermal resistance between the chips. Additionally,since the connections are formed between the chips, a visual inspectionof the bond integrity is generally not possible.

[0007] Accordingly, there is a pronounced need for an interconnectionapparatus and method for semiconductor packages comprised of verticalchip stacks that permits relatively short interconnecting lengths toextend between chip bonding pads that are patterned on the chips atrelatively high densities, while avoiding the thermal incompatibilitydifficulties present in prior art methods, which is easily adaptable tosmall as well as larger production runs of semiconductor packages.

SUMMARY OF THE INVENTION

[0008] The present invention is directed to a leadless andinterconnected semiconductor package. The package includes a firstsemiconductor chip with a second semiconductor chip positioned on thefirst chip to form a vertically stacked package. Each semiconductor chipfurther includes a plurality of bond pads disposed on an active surfaceof the chips that are electrically coupled to the active elements formedwithin each chip. Interconnections between the bond pads on each chipare formed by metallized layers disposed on the package that extendbetween corresponding bond pads and join a plurality of castellationsdisposed along sides of the package to form a plurality of leadlessinput/output locations for the package. In one aspect of the invention,the castellations include generally planar metallized portions extendingdownwardly to a lower surface of the package. In another aspect, thecastellations include semi-cylindrical metallized portions that projectinwardly into sides of the package. In a further aspect, a dielectricinsulator is positioned between the first and second chips andpositioned on a base of the package. In still a further aspect, asemiconductor chip with a photosensitive device formed therein includesat least one optical layer positioned on the photosensitive device. Aplurality of bond pads are positioned on the chip that are electricallycoupled to the photosensitive device on the chip. Castellations extendoutwardly from the bond pads to form a plurality of leadlessinput/output locations for the package.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009]FIG. 1 is a partial cross sectional view of a vertically stackedsemiconductor package according to the prior art.

[0010]FIG. 2 is a plan view of a vertically stacked, leadlesssemiconductor package according to an embodiment of the invention.

[0011]FIG. 3 is a side view of a vertically stacked, leadlesssemiconductor package according to an embodiment of the invention.

[0012] FIGS. 4(a) through 4(k) are partial cross sectional views of avertically stacked, leadless semiconductor package that show the stepsin a method of fabrication according to an embodiment of the invention.

[0013]FIG. 5 is a plan view of a vertically stacked, leadlesssemiconductor package according to another embodiment of the invention.

[0014]FIG. 6 is a side view of a vertically stacked, leadlesssemiconductor package according to another embodiment of the invention.

[0015] FIGS. 7(a) through 7(h) are partial cross sectional views of avertically stacked, leadless semiconductor package that show the stepsin a method of fabrication according to another embodiment of theinvention.

[0016]FIG. 8 is a plan view of a vertically stacked, leadlesssemiconductor package according to still another embodiment of theinvention.

[0017]FIG. 9 is a side view of a vertically stacked, leadlesssemiconductor package according to still another embodiment of theinvention.

[0018] FIGS. 10(a) through 10(i) are partial cross sectional views of avertically stacked, leadless semiconductor package that show the stepsin a method of fabrication according to still another embodiment of theinvention.

[0019]FIG. 11 is a plan view of a vertically stacked, leadlesssemiconductor package according to yet another embodiment of theinvention.

[0020]FIG. 12 is a side view of a vertically stacked, leadlesssemiconductor package according to yet another embodiment of theinvention.

[0021] FIGS. 13(a) through 13(f) are partial cross sectional views of avertically stacked, leadless semiconductor package that show the stepsin a method of fabrication according to yet another embodiment of theinvention.

DETAILED DESCRIPTION OF THE INVENTION

[0022] The present invention is generally directed to a method andapparatus for forming vertically stacked integrated circuit packages.More particularly, the invention relates to a chip interconnection andleadless packaging apparatus and method for semiconductor devices. Manyof the specific details of certain embodiments of the invention are setforth in the following description and in FIGS. 2 through 13 to providea thorough understanding of such embodiments. One skilled in the artwill understand, however, that the present invention may be practicedwithout several of the details described in the following description.

[0023]FIG. 2 is a plan view of a vertically stacked, interconnected andleadless semiconductor package 20 according to an embodiment of theinvention. A first chip 24 includes a plurality of active elementsformed therein, which are electrically coupled to a plurality of bondpads 23 disposed on an active surface of the chip 24. The bond pads 23are positioned on a peripheral region of the chip 24, and are structuredto form an electrically conductive interface with other chips ordevices. A second chip 22 similarly includes a plurality of activeelements that are electrically coupled to a plurality of bond pads 21disposed on an active surface of the chip 22. The bond pads 21 arepositioned on a peripheral region of the chip 22, and are alsostructured to form electrically conductive interfaces with other chipsor devices. The second chip 22 is positioned on the first chip 24 toform a vertically stacked arrangement, with electrical interconnections25 extending between the bond pads 23 on the first chip 24 and the bondpads 21 on the second chip 22. The interconnections 25 generally extendfrom the bond pads 23 on the first chip 24 across the peripheral regionof first chip 24 then downwardly along a side of the first chip 24 toelectrically couple with the bond pads 21 on the second chip 22. Thepackage 20 further includes a plurality of castellations 26 that areelectrically coupled to the interconnections 25, which extend outwardlyfrom the bond pads 23.

[0024]FIG. 3 is a side view of the semiconductor package 20, which showsthe castellations 26 in greater detail. The castellations 26 aregenerally straight, planar conductive members that extend downwardlyfrom the interconnections 25 along a side 28 of the chip 24 to a lowersurface 29 of the package 20. The castellations 26 thus constitute aplurality of leadless input/output locations for the package 20 thatpermit electrical coupling of the package 20 to other external circuitsor devices (not shown). The interconnections 25 and the castellations 26may be comprised of various metals, including aluminum and aluminumalloys, or copper and its various alloys that are deposited on thesurfaces of the first chip 24 and the second chip 22 by variousmetallization processes. Alternatively, the interconnections 25 and thecastellations 26 may be comprised of gold, or various refractory metals,such as titanium, tungsten, tantalum, molybdenum, or some otherconductive material. Still other means are available to form theinterconnections. For example, wire bond elements may extend between thebond pads 23 on the first chip 24 and the bond pads 21 on the secondchip 22 to electrically couple the first chip 24 to the second chip 22.The wire bond elements may be attached to the bond pads 21 and the bondpads 23 by spot welding, reflow soldering, or by depositing a conductiveadhesive to the bond pads 21 and the bond pads 23 and immersingrespective ends of the wire bond elements in the conductive adhesive.

[0025] Still referring to FIGS. 2 and 3, undesired electricalcommunication between the chips 22 and 24 is prevented through theapplication of various dielectric layers (not shown in FIGS. 2 and 3)that are interposed between the first chip 24 and the second chip 22during the fabrication of the package 20. Additional dielectric layers(also not shown in FIGS. 2 and 3) are applied to the package 20 prior tothe application of the interconnections 25 to electrically isolate theportions of the interconnections 25 extending between the bond pads 21and 23. Similarly, the portions of the castellations 26 extending fromthe bond pads 23 to the lower surface 29 are electrically isolated fromthe chip 24 by an additional dielectric layer. Finally, a dielectriclayer (also not shown in FIGS. 2 and 3) may be applied to the package 20that substantially overlays the first chip 24 and the interconnections25, leaving the castellations 26 at least partially exposed on the side28. The various dielectric layers thus described will be discussed ingreater detail below.

[0026] FIGS. 4(a) through 4(m) are partial cross-sectional views of thevertically stacked, interconnected and leadless semiconductor package 20that show the steps in a method of fabricating the package 20 accordingto an embodiment of the invention. In FIG. 4(a), a wafer 30 thatincludes a plurality of first chips 24 formed therein is shown. Aspreviously described above in connection with FIGS. 2 and 3, each of thefirst chips 24 has a plurality of bond pads 23 exposed at an uppersurface 31 of the wafer 30 that comprise the input and output locationsfor each of the first chips 24. In FIG. 4(b), a photoresist layer 32 isapplied to the wafer 30 of FIG. 4(a). The photoresist layer 32 may beuniformly applied to the upper surface 31 of the wafer 30 by suitablemeans, such as by spinning the wafer 30 after depositing a photoresistmaterial to the upper surface 31. The photoresist layer 32 may then bebaked to adhere the photoresist layer 32 to the upper surface 31,whereupon the layer 32 may then be exposed through a photomask (notshown) to obtain a predetermined photoresist pattern on the surface 31.The photoresist layer 32 is then washed to remove unaffected portions ofthe layer 32, to obtain photoresist elements 33 that overlay the bondpads 23, as shown in FIG. 4(c).

[0027]FIG. 4(d) shows an adhesive layer 34 applied to the upper surface31 of the wafer 30 that extends between the photoresist elements 33. Theadhesive layer 34 forms a dielectric layer and may be comprised, forexample, of a dielectric adhesive that is suitable for the surfacemounting of electronic components, such as CircuitSAF™ MA-420 surfacemount adhesive, manufactured by the Lord Chemical Products Co. ofIndianapolis, Ind., although other suitable alternatives exist. Forexample, the stacked semiconductor chips may be adhesively joined usingan adhesive-backed bonding film, such as the LE surface bonding tapemanufactured by the Lintec Corporation of Tokyo, Japan.

[0028] A plurality of second chips 22 are positioned on the uppersurface 31 of the wafer 30 at locations between the bond pads 23 andretained on the surface 31 by the previously applied adhesive layer 34,as shown in FIG. 4(e). A photoresist layer 35 is then deposited on theupper surface 31 of the wafer 30 and upon the second chips 22. Thephotoresist layer 35 is subsequently exposed through a suitablephotomask (not shown) and washed to remove the unaffected portions ofthe layer 35 to leave photoresist elements 40, which extend over thebond pads 23 of the wafer 30. The unaffected portions of the layer 35also form photoresist elements 43 that overlay the bond pads 21 of thechips 22, as shown in FIG. 4(f).

[0029] Referring now to FIG. 4(g), a first dielectric layer 42 isdisposed on the second chips 22 that extends between the photoresistelements 43 on the bond pads 21, and further extends over the secondchips 22 to abut the photoresist elements 40. The first dielectric layer42 may be comprised of a non-electrically conductive epoxy material, ormay be further comprised of a polyimide or benzocyclobutene material,although other alternatives exist.

[0030] Turning now to FIG. 4(h), the wafer 30 may now be thinned byremoving wafer material from a lower surface 46 of the wafer 30, inpreparation for the wafer singulation, which will be described ingreater detail below. The wafer 30 may be thinned, for example, bybackgrinding the lower surface 46 of the wafer 30 to achieve apredetermined wafer thickness. Alternatively, the wafer 30 may bethinned by wet spin etching the lower surface 46, or bychemical-mechanical planarization of the lower surface 46, or by someother means. Still referring to FIG. 4(h), the wafer 30 is singulatedalong planes 44 to form a plurality of individual units 48, whichinclude a single first chip 24 that underlies the second chip 22. Thewafer singulation may be performed by various cutting methods, includingshearing or punching the wafer 30 to form separated units 48, or byrouting the wafer 30 to form the separated units 48 from the wafer 30.Alternatively, the wafer 30 may be diced by a rotating blade to form theseparated units 48.

[0031] For clarity of illustration, FIGS. 4(i) through 4(m) show theremaining processing steps applied to the separated unit 48. Althoughthese processing steps show subsequent operations applied to the unit48, it is understood that at least a portion of the operations shown inFIGS. 4(i) through 4(m) may be applied prior to the singulation of thewafer 30 into separated units 48. Turning now to FIG. 4(i), a dielectriclayer 52 is applied to opposing faces 50 of the unit 48. The dielectriclayer 52 may be comprised of a non-electrically conductive epoxymaterial, or alternatively, for example, the dielectric layer 52 may becomprised of a polyimide or benzocyclobutene material. The photoresistelements 40, 43 and 33 may now be stripped to expose the bond pads 23and the bond pads 21, as shown in FIG. 4(j). The photoresist elements40, 43 and 33 may be stripped from the unit 48 using conventionalphotoresist stripping methods. For example, a wet chemical strippingprocess, or a dry plasma stripping process may be used.

[0032] Still referring to FIG. 4(j), a photoresist layer is deposited onthe package 48 that is exposed through a suitable photomask (not shown)and washed to remove the unaffected areas to yield a photoresist element54, which is positioned between the bond pads 21 of the second chip 22.

[0033] Turning now to FIG. 4(k), metallization layers 56 are applied tothe package 48 to form conductive, interconnecting elements between thebond pads 23 on the first chip 24 and the bond pads 21 on the secondchip 22. The metallization layers 56 also extend over the faces 50 toform a plurality of castellations. The metallization layer 54 may becomprised of aluminum, copper, or various alloys of these metals.Alternatively, gold, or various refractory metals may also be used. Themetallization layer 56 may be applied to the package 48 using vacuumevaporation, sputter deposition, chemical vapor deposition (CVD)methods, or some other means.

[0034]FIG. 4(l) shows the package 48 after the photoresist element 54has been stripped. A second dielectric layer 58 may then be applied tothe package 48 that extends over the first chip 24 and the second chip22 to at least partially encapsulate the package 48, as shown in FIG.4(m). The second dielectric layer 58 may be comprised of anon-electrically conductive epoxy material, or may be comprised ofpolyimide or benzocyclobutene material, although other alternativesexist.

[0035] The foregoing embodiment allows a pair of stacked semiconductorchips to be interconnected by a plurality of metallization layers thatextend from the bond pads on one semiconductor chip the bond pads on anadjacent semiconductor chip. The interconnections thus formedadvantageously permit the semiconductor chips that comprise the stack tobe coupled by relatively short interconnections, thus minimizing theintroduction of parasitic capacitance and/or inductance and signalpropagation delays. Further, bond integrity difficulties associated withdifferent thermal coefficients of expansion between the chips comprisingthe packages are minimized by advantageously forming theinterconnections on the exterior surfaces of the chips, rather thanbetween abutting chip surfaces. Still other advantages are present inthe foregoing embodiment. For example, the bond pad pitch may beincreased beyond that generally achievable using wire bonding methods,or TAB. Further, the externally positioned interconnections andcastellations permit the integrity of these connecting portions to bevisually inspected subsequent to formation.

[0036]FIG. 5 is a plan view of a vertically stacked, interconnected andleadless semiconductor package 60 according to another embodiment of theinvention. As in the previous embodiment, a first chip 24 includes aplurality of bond pads 23 disposed on an active surface of the chip 24,which are positioned on a peripheral region of the chip 24. A secondchip 22 similarly includes a plurality of bond pads 21 disposed on anactive surface of the chip 22, which are positioned on a peripheralregion of the chip 22. The second chip 22 is positioned on the firstchip 24 to form a vertically stacked arrangement, with the electricalinterconnections 25 extending from the bond pads 21 on the second chip22 and across the peripheral region of second chip 22 and downwardlyalong a side of the second chip 22 to electrically couple with the bondpads 23 on the first chip 24. The package 20 includes a plurality ofcastellations 66 that are electrically coupled to the interconnections25, which extend outwardly from the bond pads 23. The castellations 66further include semi-cylindrical termination portions 68 that projectinwardly into the edge 27 of the first chip 24.

[0037]FIG. 6 is a side view of the semiconductor package 60, which showsthe castellations 66 in greater detail. The castellations 66 extenddownwardly from the interconnections 25 along a side 28 of the chip 24to a lower surface 29 of the package 20. The castellations 66 form aplurality of leadless input/output locations for the package 60 thatpermit the package 60 to be electrically coupled to other externalcircuits or devices (not shown). As in the previous embodiment, theinterconnections 25 and the castellations 66 may be comprised of variousmetals, including aluminum and aluminum alloys, or copper and itsvarious alloys that are deposited on the surfaces of the first chip 24and the second chip 22 by various metallization processes.Alternatively, the interconnections 25 and the castellations 66 may becomprised of gold, or various refractory metals, such as titanium,tungsten, tantalum or molybdenum.

[0038] FIGS. 7(a) through 7(h) are partial cross-sectional views of thevertically stacked, interconnected and leadless semiconductor package 60that show the steps in a method of fabricating the package 60 accordingto an embodiment of the invention. Several of the steps in the method offabricating the package 60 are similar to the steps illustrated in FIGS.4(a) through 4(g), as discussed in connection with a previousembodiment. For brevity, these steps will not be discussed further inconnection with the present embodiment.

[0039]FIG. 7(a) shows a partial, cross sectional view of a wafer 30 thatincludes a plurality of first chips 24 formed therein. The plurality offirst chips 24 further includes a plurality of bond pads 23 exposed atan upper surface 31 of the wafer 30. The bond pads 23 are covered byphotoresist elements 33 that are deposited by the photo-patterningprocess described earlier. An adhesive layer 34 is disposed on the uppersurface 31 and retains a second chip 22 on the upper surface 31. Thesecond chip 22 further includes a plurality of bond pads 21 that aresimilarly covered by photoresist elements 43. A first dielectric layer42 is disposed on the second chip 22 that extends over the chip 22 toabut a photoresist element 40 disposed on a portion of the adhesivelayer 34. An opening 70 projects through the wafer 30 along an axis 71that is located approximately between the bond pads 23 of adjacent firstchips 24, which may be of approximately circular cross sectional shape,although other cross sectional shapes may be used. The opening 70 may beformed by drilling the wafer 30 with a mechanical drilling device, oralternatively, the opening 70 may be formed by laser ablation, or by ionbeam or reactive ion etching the opening 70.

[0040]FIG. 7(b) shows the wafer 30 subsequent to the application of awafer thinning step. The wafer 30 may be thinned by backgrinding a lowersurface 46 of the wafer 30, or alternatively, the wafer 30 may bethinned using the methods for wafer thinning described earlier.Following the wafer thinning step, the wafer 30 is singulated by cuttingthe wafer 30 along a plane 72 that extends through the axis 71 to form aplurality of individual units 72. The individual units 72 thus formedare comprised of a single first chip 24 bonded to a second chip 22. Forclarity of illustration, the following description will address furtherprocessing steps as applied to the single unit 72, which is shown inFIGS. 7(c) through 7(h).

[0041] Subsequent to the singulation of the wafer 30 into individualunits 72, a plurality of castellations 66 are formed along the edge 67of each unit 72 that are approximately semicircular in cross sectionalshape, as shown in FIG. 7(c), but more clearly shown with referenceagain to FIGS. 5 and 6. A dielectric layer 73 is next deposited on theinner surfaces of the castellations 66, as shown in FIG. 7(d). Thephotoresist elements 33, 40 and 43 are then stripped from the affectedsurfaces of the unit 72, and an additional photoresist element 54 ispatterned on the unit 72, as shown in FIG. 7(e).

[0042] Turning now to FIG. 7(f), metallization layers 56 are depositedon the unit 72 that extend from the bond pads 21 on the second chip 22to the bond pads 23 on the first chip 24, and downwardly into thecastellations 66, as shown in FIG. 7(g). A second dielectric layer 58may then be applied to the unit 72 that extends over the second chip 22and covers at least a portion of the metallization layers 56, as shownin FIG. 7(h).

[0043] In addition to the advantages described in connection with theprevious embodiment, the foregoing embodiment advantageously permits thepackage 60 to be positioned on an underlying substrate having aplurality of upwardly projecting conductive members that may be receivedby the semicircular castellations of the package 60. As a result,improved electrical and mechanical connections between the package 60and the underlying substrate may be obtained.

[0044]FIG. 8 is a plan view of a vertically stacked, interconnected andleadless semiconductor package 80 according to still another embodimentof the invention. As in the previous embodiments, a first chip 24includes a plurality of bond pads 23 disposed on an active surface ofthe chip 24. A second chip 22 includes a plurality of bond pads 21disposed on an active surface of the chip 24. The second chip 22 ispositioned on the first chip 24 to form a vertically stackedarrangement, with electrical interconnections 25 extending between thebond pads 23 on the first chip 24 and the bond pads 21 on the secondchip 22. The package 80 includes a plurality of castellations 26 thatare electrically coupled to the interconnections 25, which extendoutwardly from the bond pads 23.

[0045] Referring now to FIG. 9, a side view of the semiconductor package80 is shown. The castellations 26 are electrically coupled to theinterconnections 25 and extend downwardly from the interconnections 25along a side 28 of the chip 24 to a lower surface 29 of the package 80.A first insulator 82 is positioned between the first chip 22 and thesecond chip 24 to prevent electrical communication between the firstchip 24 and the second chip 22. A second insulator 84 is positioned onthe lower surface 29 of the first chip 24 to prevent electricalcommunication between the first chip 24 and an underlying substrate (notshown) that supports the package 80. The first insulator 82 and thesecond insulator 84 may be comprised of a dielectric polymer, or a glasssubstrate that is attached to the first chip 24 and the second chip 22,although other insulating materials may be used. For example, the firstinsulator 82 and the second insulator 84 may be comprised of a silicondioxide layer formed on the first chip 24 and the second chip 22 bythermal oxidation. Alternatively, the first insulator 82 and the secondinsulator 84 may be comprised of a variety of spin-on-glass compounds,such as ACCUGLASS, which is manufactured by Honeywell, Inc. ofMinneapolis, Minn.

[0046] FIGS. 10(a) through 10(i) are partial cross-sectional views ofthe vertically stacked, interconnected and leadless semiconductorpackage 80 that show the steps in a method of fabricating the package 80according to still another embodiment of the invention. In FIG. 10(a), aplurality of first chips 24 are formed in a wafer 30, with each of thefirst chips 24 having a plurality of bond pads 23 that are exposed at anupper surface 31 of the wafer 30. In FIG. 10(b), a plurality of firstchips 22 having first insulators 82 disposed on a lower surface 83 ofthe first chips 22 are positioned on the upper surface 31 of the wafer30. The first insulators 82 may be adhesively joined to the uppersurface 31 by a dielectric adhesive, such as a polyimide adhesive, orbenzocyclobutene.

[0047] In FIG. 10(c), photoresist elements 40 are formed on the uppersurface 31 that overlay and extend between the bond pads 23. Similarly,photoresist elements 43 are formed that overlay the bond pads 43 on thefirst chips 22. The photoresist elements 40 and 43 are formed fromphotoresist materials that are applied to the surfaces and patterned byexposure of the photoresist material through a photomask, as describedearlier. A first dielectric layer 42 is disposed on the first chips 22between the photoresist elements 43 and extends over the first chips 22to abut the photoresist elements 40, as shown in FIG. 10(d).

[0048] In FIG. 10(e), the wafer 30 is thinned by removing material fromthe lower surface 46 of the wafer 30 by any of the wafer thinningmethods previously described. A second insulator 84 may now be appliedto the lower surface 46 of the thinned wafer 30. The wafer 30 may thenbe singulated to form the individual units 85. The photoresist elements40 and 43 are then stripped from the singulated unit 85, as shown inFIG. 10(f). For clarity of illustration, FIGS. 10(f) through 10(i) showthe remaining processing steps applied to the individual unit 85.Although these processing steps show subsequent operations applied tothe unit 85, it is understood that at least a portion of the operationsshown in FIGS. 10(f) through 10(i) may be applied prior to thesingulation of the wafer 30 into the units 85.

[0049] Turning now to FIG. 10(g), a layer of photoresist 86 is appliedto the unit 85 that is patterned to leave opposing ends 50 of the unit85 exposed. A dielectric layer 52 may then be deposited on the ends 50that extends from the bond pads 23 downwardly to a lower surface 87 ofthe second insulator 84. The photoresist layer 86 may then be stripped,and metallization layers 56 applied to the unit 85 that extend from thebond pads 21 on the first chip 22 to the bond pads 23 on the second chip24 and downwardly over the dielectric layers 52 to the lower surface 87of the second insulator 84 to form a plurality of castellations 26. Aphotoresist element 54 has been formed at this step to prevent themetallization layers 56 from extending across the first dielectric layer42. The photoresist element 54 may subsequently be stripped from theunit 85, and a second dielectric layer 58 may be applied over the firstchip 22 and the second chip 24 to leave the plurality of castellations26 exposed, as shown in FIG. 10(i).

[0050] The inclusion of insulating layers as described in the presentembodiment advantageously permits semiconductor chips that have anactive rear face that opposes the active front face upon which the bondpads are disposed to be assembled into a vertical stack without theforming undesired electrical conduction paths between the chipscomprising the stack, or between the package and other extended portionsof an electronic system.

[0051]FIG. 11 is a plan view of a leadless semiconductor package 90according to yet another embodiment of the invention. In contrast to theprevious embodiments, the semiconductor chip 91 has a photosensitivedevice 92 formed therein, which may include any device that sensesincident light by the photoelectric effect. For example, thephotosensitive device 92 may be comprised of a charge coupled device(CCD) array, which is further comprised of a plurality of individualelements, each capable of accumulating the electrons produced by theincident photons within a non-conductive boundary while the element isexposed to the incident light, and releasing the accumulated electronsafter the exposure is interrupted. Alternatively, the photosensitivedevice 92 may be comprised of a complementary metal oxide semiconductor(CMOS) imaging device. The photosensitive device 92 may be overlaid byone or more optical layers 93, which may be comprised, for example oflayers generally having a low index of refraction that are transparentto visible light, or layers that block certain portions of the visiblespectrum, such as red, green and blue optical filters that may be usedto form a color image from the CCD elements previously described. Stillfurther, the optical layers 93 may be used to block the infrared, orultraviolet portions of the electromagnetic spectrum. Still referring toFIG. 11, the chip 91 includes a plurality of bond pads 23 that arecoupled to the active elements in the chip 91, and comprise the inputand output locations for the chip 91. The bond pads 23 are electricallycoupled to a plurality of castellations 26 that extend from the bondpads 23 to an edge 27 of the chip 91.

[0052] Referring now to FIG. 12, a side view of the semiconductorpackage 90 is shown. The castellations 26 extend downwardly from thebond pads 23 along a side 28 of the chip 91 to a lower surface 29 of thepackage 90. As in the embodiments previously described, thecastellations 26 permit the package 90 to be electrically coupled toother circuits and/or devices (not shown).

[0053] FIGS. 13(a) through 13(f) are partial cross-sectional views ofthe leadless semiconductor package 90 that show the steps in a method offabricating the package 90 according to an embodiment of the invention.FIG. 13(a) shows a wafer 30 that includes a plurality of photosensitivedevices 92 formed therein. Each of the devices 92 has a plurality ofadjacent bond pads 23 that are exposed at an upper surface 31 of thewafer 30 that comprise the input and output locations for each of thephotosensitive devices 92. In FIG. 13(b), an optical layer 93 isdisposed on each of the photosensitive devices 92. The optical layer 93may include one or more layers of an appropriately sized opticallytransparent material that are positioned over each of the photosensitivedevices 92, and retained on the photosensitive device 92 with anoptically transparent adhesive. Alternatively, the optical layer 93 maybe formed by spin coating one or more layers of an optically transparentmaterial onto the surfaces of the photosensitive devices 93, or bysputtering an optically transparent material onto the surfaces of thedevices 93. Further, the optical layer 93 may be also be formed bygrowing an epitaxial layer of a semiconductor material onto the surfacesof the devices 93.

[0054] Turning now to FIG. 13(c), a plurality of drains 94 are cut intothe wafer 30 along planes 99, which are located between the bond pads 23of adjacent devices 93. The drains 94 project into the wafer 30 to adepth of at least about one-half thickness of the wafer 30. Dielectriclayers 95 are then deposited in the drains 94 that extend downwardlyinto the drains 94 and over a portion of the upper surface 31 to abutthe bond pads 23. A dielectric layer 96 is similarly deposited on theupper surface 31 that abuts the optical layers 93 and the bond pads 23,as shown in FIG. 13(d).

[0055] Referring to FIG. 13(e), metallization layers 97 are depositedover the dielectric layers 95 that further extend over the bond pads 23and abut the dielectric layers 96. The upper surfaces 98 of the opticallayers 93 may now be optionally subjected to a surface planarization toobtain a uniformly flat optical surface, and to further thin the layers93. The wafer 30 may now be thinned by backgrinding the wafer 30 toremove material from a lower surface 46 of the wafer 30. Thebackgrinding proceeds through the lower surface 46 and towards the uppersurface 31 to a distance “d” so that the wafer 30 is singulated intoseparate packages 90, as shown in FIG. 13(f). Alternatively, other wafersingulation methods may be used to singulate the wafer 30 into theseparate packages 90. Still referring to FIG. 13(f), a dielectric layer100 that abuts the optical layers 93 is deposited over the castellations26.

[0056] In addition to the advantages previously discussed in connectionwith other embodiments of the disclosed invention, the foregoingembodiment allows a photosensitive semiconductor package to be formedwith reduced size, which advantageously has a reduced cross sectionalthickness.

[0057] The above description of illustrated embodiments of the inventionis not intended to be exhaustive or to limit the invention to theprecise form disclosed. While specific embodiments of, and examples of,the invention are described in the foregoing for illustrative purposes,various equivalent modifications are possible within the scope of theinvention as those skilled within the relevant art will recognize. Forexample, although a package having two semiconductor chips verticallystacked and interconnected is disclosed, it is understood that three ormore semiconductor chips may be combined and interconnected in themanner described. Further, although the interconnections and thecastellations are described as separate elements, it is understood thatthe castellations and the interconnections are disposed on the chips asa continuous segment of conductive material. Moreover, the variousembodiments described above can be combined to provide furtherembodiments. Accordingly, the invention is not limited by thedisclosure, but instead the scope of the invention is to be determinedentirely by the following claims.

1. A semiconductor package, comprising: a first semiconductor chiphaving an upper surface; a second semiconductor chip having an uppersurface and an opposing lower surface, the lower surface of the secondchip being positioned on the upper surface of the first chip to definean exposed portion of the upper surface of the first chip, the firstchip further including a first plurality of bond pads disposed on theexposed portion, and the second chip further including a secondplurality of bond pads disposed on the upper surface of the second chip;a plurality of interconnections that extend from the first plurality ofbond pads to the second plurality of bond pads, the interconnectionsbeing disposed on selected portions of the first and second chips toelectrically couple the first and second chips; and a plurality ofcastellations disposed on selected portions of the first chip thatextend outwardly from the first plurality of bond pads to form leadlessinput/output locations for the package.
 2. The semiconductor packageaccording to claim 1 wherein the second semiconductor chip is furthercomprised of a peripheral surface that extends between the upper and thelower surface, and further wherein the plurality of interconnectionsdisposed on selected portions of the first and second chips extendinwardly along the upper surface of the first chip from the firstplurality of bond pads and extend upwardly along the peripheral surfaceto the second plurality of bond pads.
 3. The semiconductor packageaccording to claim 1 wherein the first semiconductor chip is furthercomprised of a lower surface having a lower edge, the lower surfaceopposing the upper surface and having a peripheral surface that extendsbetween the upper and the lower surfaces.
 4. The semiconductor packageaccording to claim 3 wherein the plurality of castellations is furthercomprised of a plurality of planar members that extend upwardly from thelower edge and along the peripheral surface to the first plurality ofbond pads.
 5. The semiconductor package according to claim 3 wherein theplurality of castellations is further comprised of a plurality ofsemi-circular members each having an axis that is approximately parallelto the peripheral surface that extend inwardly into the peripheralsurface and upwardly from the lower edge to the first plurality of bondpads.
 6. The semiconductor package of claim 1, further comprising adielectric layer interposed between the plurality of interconnectionsand the first and second chips.
 7. The semiconductor package of claim 1,further comprising a dielectric layer interposed between the pluralityof castellations and the first chip.
 8. The semiconductor package ofclaim 1, further comprising a dielectric layer disposed on the secondchip that substantially encapsulates the second chip and extends onto atleast a portion of the first chip.
 9. The semiconductor packageaccording to claim 3, further comprising an insulating layer disposed onthe lower surface of the first chip.
 10. The semiconductor packageaccording to claim 9, wherein the insulating layer is comprised of adielectric polymer.
 11. The semiconductor package according to claim 9,wherein the insulating layer is comprised of a glass substrate.
 12. Thesemiconductor package of claim 1, further comprising an insulating layerinterposed between the first and second chips.
 13. The semiconductorpackage according to claim 12, wherein the insulating layer is furthercomprised of a dielectric adhesive.
 14. The semiconductor packageaccording to claim 12, wherein the insulating layer is further comprisedof a dielectric polymer adhesively joined to the upper surface of thefirst chip and the lower surface of the second chip.
 15. Thesemiconductor package according to claim 12, wherein the insulatinglayer is further comprised of a glass substrate adhesively joined to theupper surface of the first chip and the lower surface of the secondchip.
 16. The semiconductor package according to claim 12, wherein theinsulating layer is further comprised of a self-adhering dielectricfilm.
 17. The semiconductor package according to claim 1 wherein theplurality of interconnections are further comprised of a plurality ofmetallic films.
 18. The semiconductor package according to claim 17wherein the plurality of metallic films are comprised of aluminum. 19.The semiconductor package according to claim 17 wherein the plurality ofmetallic films are comprised of copper.
 20. The semiconductor packageaccording to claim 17 wherein the plurality of metallic films arecomprised of a refractory metal.
 21. The semiconductor package accordingto claim 1 wherein the plurality of interconnections further comprises aplurality of bonding wires that extend from the first plurality of bondpads to the second plurality of bond pads.
 22. The semiconductor packageaccording to claim 1 wherein the plurality of castellations are furthercomprised of a plurality of metallized films.
 23. The semiconductorpackage according to claim 22 wherein the plurality of metallic filmsare comprised of aluminum.
 24. The semiconductor package according toclaim 22 wherein the plurality of metallic films are comprised ofcopper.
 25. The semiconductor package according to claim 22 wherein theplurality of metallic films are comprised of a refractory metal.
 26. Asemiconductor package, comprising: a first semiconductor chip having anupper surface; a second semiconductor chip having an upper surface andan opposing lower surface, the lower surface of the second chip beingpositioned on the upper surface of the first chip to define an exposedportion of the upper surface of the first chip, the first chip furtherincluding a first plurality of bond pads disposed on the exposedportion, and the second chip further including a second plurality ofbond pads disposed on the upper surface of the second chip; a pluralityof wire bond elements that extend from the first plurality of bond padsto the second plurality of bond pads to electrically couple the firstand second chips; and a plurality of castellations disposed on selectedportions of the first chip that extend outwardly from the firstplurality of bond pads to form leadless input/output locations for thepackage.
 27. The semiconductor package according to claim 26 wherein thefirst semiconductor chip is further comprised of a lower surface havinga lower edge, the lower surface opposing the upper surface and having aperipheral surface that extends between the upper and the lowersurfaces.
 28. The semiconductor package according to claim 27 whereinthe plurality of castellations is further comprised of a plurality ofplanar members that extend upwardly from the lower edge and along theperipheral surface to the first plurality of bond pads.
 29. Thesemiconductor package according to claim 27 wherein the plurality ofcastellations is further comprised of a plurality of semi-circularmembers each having an axis that is approximately parallel to theperipheral surface that extend inwardly into the peripheral surface andupwardly from the lower edge to the first plurality of bond pads. 30.The semiconductor package of claim 26, further comprising a dielectriclayer interposed between the plurality of castellations and the firstchip.
 31. The semiconductor package of claim 26, further comprising adielectric layer disposed on the second chip that substantiallyencapsulates the second chip and extends onto at least a portion of thefirst chip.
 32. The semiconductor package according to claim 27, furthercomprising an insulating layer disposed on the lower surface of thefirst chip.
 33. The semiconductor package according to claim 32, whereinthe insulating layer is comprised of a dielectric polymer.
 34. Thesemiconductor package according to claim 32, wherein the insulatinglayer is comprised of a glass substrate.
 35. The semiconductor packageof claim 26, further comprising an insulating layer interposed betweenthe first and second chips.
 36. The semiconductor package according toclaim 35, wherein the insulating layer is further comprised of adielectric adhesive.
 37. The semiconductor package according to claim35, wherein the insulating layer is further comprised of a dielectricpolymer adhesively joined to the upper surface of the first chip and thelower surface of the second chip.
 38. The semiconductor packageaccording to claim 35, wherein the insulating layer is further comprisedof a glass substrate adhesively joined to the upper surface of the firstchip and the lower surface of the second chip.
 39. The semiconductorpackage according to claim 35, wherein the insulating layer is furthercomprised of a self-adhering dielectric film.
 40. The semiconductorpackage according to claim 26 wherein the plurality of castellations arefurther comprised of a plurality of metallized films.
 41. Thesemiconductor package according to claim 40 wherein the plurality ofmetallic films are comprised of aluminum.
 42. The semiconductor packageaccording to claim 40 wherein the plurality of metallic films arecomprised of copper.
 43. The semiconductor package according to claim 40wherein the plurality of metallic films are comprised of a refractorymetal.
 44. A package for a photosensitive device capable of sensingincident light, comprising: a semiconductor chip having an upper surfacethat supports the photosensitive device, the chip having a plurality ofbond pads exposed at the upper surface that are coupled to the device;at least one optical layer disposed on the photosensitive device; and aplurality of castellations disposed on selected portions of the chipthat extend outwardly from the bond pads to form a plurality of leadlessinput/output locations for the package.
 45. The package according toclaim 44 wherein the semiconductor chip is further comprised of anopposing lower surface having a lower edge and a peripheral surface thatextends between the upper surface and the lower surface.
 46. The packageaccording to claim 45 wherein the plurality of castellations is furthercomprised of a plurality of planar members extending upwardly from thelower edge and along the peripheral surface to the bond pads.
 47. Thepackage according to claim 45 wherein the plurality of castellations isfurther comprised of a plurality of semi-circular members each having anaxis that is approximately parallel to the peripheral surface thatextend inwardly into the peripheral surface and upwardly from the loweredge to the plurality of bond pads.
 48. The package of claim 44, furthercomprising a dielectric layer interposed between the castellations andthe chip.
 49. The package according to claim 45, further comprising aninsulating layer disposed on the lower surface of the chip.
 50. Thepackage according to claim 49, wherein the insulating layer is comprisedof a dielectric polymer.
 51. The package according to claim 49, whereinthe insulating layer is comprised of a glass substrate.
 52. The packageaccording to claim 44 wherein the plurality of castellations are furthercomprised of a plurality of metallized films.
 53. The package accordingto claim 52 wherein the plurality of metallic films are comprised ofaluminum.
 54. The package according to claim 52 wherein the plurality ofmetallic films are comprised of copper.
 55. The package according toclaim 52 wherein the plurality of metallic films are comprised ofcopper.
 56. The package according to claim 52 wherein the plurality ofmetallic films are comprised of a refractory metal.
 57. A method forforming a leadless, interconnected semiconductor package, comprising:disposing a second semiconductor chip onto a first semiconductor chip,each chip having a plurality of exposed bond pads; forming a pluralityof interconnections that extend from bond pads on the first chip tocorresponding bond pads on the second chip; and forming a plurality ofcastellations that extend from the bond pads on the first chip.
 58. Themethod according to claim 57 wherein the step of disposing is furthercomprised of bonding the second chip to the first chip with an adhesive.59. The method according to claim 57 wherein the step of bonding isfurther comprised of bonding the second chip to the first chip using andouble-backed adhesive tape.
 60. The method according to claim 57wherein the step of disposing is further comprised of interposing aninsulating layer between the first and second semiconductor chips. 61.The method according to claim 57 wherein the step of forming a pluralityof interconnections further comprises: applying a dielectric layer to asurface portion of the first and the second semiconductor chips; anddepositing a metallic film on the dielectric layer.
 62. The methodaccording to claim 57 wherein the step of forming a plurality ofcastellations further comprises: applying a dielectric layer to asurface portion of the first semiconductor chip; and depositing ametallic film on the dielectric layer.
 63. The method according to claim57 further comprising: applying a dielectric layer to the secondsemiconductor chip that extends at least partially onto a surface of thefirst semiconductor chip.
 64. A method for fabricating a plurality ofvertically stacked, interconnected and leadless semiconductor packages,comprising: supporting a substrate having a plurality of firstsemiconductor chips formed therein, the first chips having a firstplurality of bond pads exposed at an upper surface of the substrate;positioning a plurality of second semiconductor chips onto thesubstrate, each second chip being positioned on a single first chip andhaving a second plurality of bond pads; depositing a plurality ofinterconnections onto the first chips and the second chips that extendbetween corresponding bond pads on the first and second chips;singulating the substrate to obtain a plurality of separatedsemiconductor packages; and depositing a plurality of castellations tothe first chips that extend outwardly from the first plurality of bondpads.
 65. The method according to claim 64 wherein the step ofpositioning is further comprised of bonding the second chips to thesubstrate using an adhesive.
 66. The method according to claim 64wherein the step of bonding is further comprised of applying one side ofa double-backed adhesive tape to the substrate; and disposing the secondchip onto an opposing side of the double-backed adhesive tape.
 67. Themethod according to claim 64 wherein the step of depositing a pluralityof interconnections further comprises: depositing a dielectric layeronto selected surface portions of the first and second chips; andforming a metallic film on the dielectric layer.
 68. The methodaccording to claim 64 wherein the step of depositing a plurality ofcastellations further comprises: depositing a dielectric layer ontoselected surface portions of the first chips; and forming a metallicfilm on the dielectric layer.
 69. The method according to claim 64wherein the step of singulating the substrate further comprises:thinning the substrate at a lower surface that opposes the upper surfaceto obtain a thinned substrate; and dicing the thinned substrate to forma plurality of separated semiconductor packages.
 70. The methodaccording to claim 64 wherein the step of singulating the substratefurther comprises: forming a plurality of holes that project through thesubstrate that are positioned between adjacent first chips; thinning thesubstrate at a lower surface that opposes the upper surface to obtain athinned substrate; and dicing the thinned substrate along a directionthat substantially bisects the holes.
 71. The method according to claim70 wherein the step of thinning the substrate is further comprised ofbackgrinding the substrate.
 72. The method according to claim 64,further comprising applying a dielectric layer to the secondsemiconductor chips that substantially encapsulates the second chips andat least partially extends onto the first chips.
 73. A method forfabricating a plurality of photosensing packages, comprising: supportinga substrate having a plurality of photosensitive devices formed on anupper surface of the substrate, each photosensitive device having aplurality of bond pads disposed on the upper surface; disposing at leastone optical layer onto the photosensitive device; forming a plurality ofdrains in the upper surface of the substrate that are positioned betweenadjacent photosensitive devices and project at least partially into thesubstrate; thinning the substrate at a lower surface that opposes theupper surface to expose the plurality of drains; and depositing aplurality of castellations onto the packages that extend outwardly fromthe plurality of bond pads.
 74. The method according to claim 73 whereinthe step of depositing a plurality of castellations further comprises:depositing a dielectric layer onto selected surface portions of thepackage; and forming a metallic film on the dielectric layer.
 75. Themethod according to claim 73 wherein the step of thinning the substratefurther comprises: forming a plurality of holes that project through thesubstrate that are positioned between adjacent photosensitive devices;backgrinding the substrate at the lower surface to obtain a thinnedsubstrate; and dicing the thinned substrate along a direction thatsubstantially bisects the holes.
 76. The method according to claim 73wherein the step of disposing at least one optical layer onto thephotosensitive device further comprises positioning an optical layeronto the photosensitive device that substantially blocks infraredradiation.
 77. The method according to claim 73 wherein the step ofdisposing at least one optical layer onto the photosensitive devicefurther comprises applying an optical layer by spin coating an opticallytransparent material onto the photosensitive device.
 78. The methodaccording to claim 77 wherein the step of applying an optical layer byspin coating an optically transparent material onto the photosensitivedevice is further comprised of planarizing a surface of the opticallayer.
 79. The method according to claim 73 wherein the step ofdisposing at least one optical layer onto the photosensitive devicefurther comprises: sputtering a layer of an optically transparentmaterial onto the photosensitive device; and planarizing the sputteredlayer to obtain an optically flat surface.
 80. The method according toclaim 73 wherein step of disposing at least one optical layer onto thephotosensitive device further comprises: growing an expitaxial layer onthe photosensitive device; and planarizing the epitaxial layer to obtainan optically flat surface.